Download Shader Model 3.0

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Product : Radeon X1800 XT
Company : ATI Technologies
Author : Ryan 'MrB' Ku and Mark 'Ratchet' Thorne
Editor : Eric 'Ichneumon' Amidon
Date : October 13th, 2005

Shader Model 3.0

Shader

It’s been a long time coming and now it has finally arrived, Shader Model 3.0 support from ATi. Ithas been a major feature selling point for nVidia that ATi now equals or betters. In ATi’s words their Shader Model 3.0 implementation is “Done Right”. By being “Done Right” they stress two features that perform well on their pixel shader architecture; flow control and 128-bit (FP32) rendering.

Model

Ultra-Threaded Pixel Shader Engine

The key to X1000’s pixel shader is their new Ultra-Threaded Pixel Shader Engine. The engine is another component that stresses efficiency in ATi’s architecture by hiding latency and avoiding wasted cycles.

The Ultra-Threaded Pixel Shader Engine is an intelligent scheduler which breaks down pixelworkload into a large number of tasks or threads to be worked on by either the Texture Address Unit/TextureUnits or the Pixel Shader Core. Really what they’ve done is taken a page out of the Xenos engineering teamplay book and applied it to the Pixel Shader units.

One key source of wasted clock cycles is when a pixel shader requires a texture value which is not readily available (not in texture cache) or the texture result hasn’t been calculated. This produces a stall which can introduce hundreds of cycles of latency. This occurred in past generations as the pixel shader core was kept waiting.

With the X1000’s Ultra-Threading Dispatch schedule this stall does not occur. If a shader program has reached an instruction that needs a texture result, the scheduler senses that the core has become idle and temporarily suspends the idle thread and assigns the free Pixel Shader Core another thread. ATi states that the pixel shadercore achieves well over 90% utilization in practice with this process.

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All temporary threads are known as “context” and are stored in a multi-ported (allows multiple simultaneous reads and writes) General Purpose Register Array. The array has a high bandwidth connection to the pixel shader cores to allow quick and seamless switching between threads.

The second source of inefficiency ATi also improved is in dynamic branching, one of the key features in the PS 3.0 model. Dynamic branching allows a program to execute different branches depending on calculated values. It can provide significant opportunities for performance boosts, such as allowing a large portion of shader code to be skipped. However, if executed improperly, it can increase workload and reduce performance as dynamic branching in pixel shaders generally destroys the parallelism of traditional graphics architectures.

To do dynamic branching “right” ATi focused on two things. First is thread size. The X1800 threads consists of small 4x4 blocks of pixels (16 pixels). By keeping the thread size small the likelihood of each pixel in the same thread running down the same path together is increased, allowing you to achieve parallelism and locality. You only need to have one shader program loaded for all of the pixels, you only have to schedule the instructions in the shader once for all of the pixels, and it's likely that any texture lookups by all of the pixels will access nearby locations in memory.

Download Shader Model 3.0

When a pixel(s) in a thread does branch down a different path, it incurs a waste of shader utlization because all of the pixels in the thread must run each possible code path resulting in redundant processing. Therefore to achieve fast branching, thread sizes should be as small as possible which ATI aimed for. The X1000 is capable of this because of its large register space that it can access quickly, and efficient caches to minimize latency.

This seems to be a distinct difference between the G70 and R5xx architecture. One used it's transistor budget for extra pixel processors and the other to decrease thread sizes (register space and caches take quite a bit transistors). This allows the G70 to perform faster when running simple shaders but hurts them when running complex SM3.0 shaders, particularly with dynamic branching.

In addition to reducing thread size ATi included a dedicated Branch Execution Unit in the Pixel Shader Core. The addition of the unit eliminates flow control overhead that comes with pixel shader branching instructions, saving several more clock cycles.


ATI provided this image to illustrate how small their thread size is in comparison to the G70 which they estimate to be around 64x64 (4096pixels). It's a little overthetop but it does show the magnitude of difference it is.

The X1800’s Ultra-Threading Dispatch scheduler is capable of tracking and distributing up to 512 threads across its four Quad Pixel Shader cores. Each core can executea shader on a 2x2 block of pixels. Therefore each thread is broken down into four 2x2 pixel blocks, which get processed in sequence by one quad shader core.

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